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INTEGRATED CIRCUITS
DATA SHEET
UAA3535HL Low power GSM/DCS/PCS multi-band transceiver
Objective specification File under Integrated Circuits, IC17 2000 Feb 17
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
FEATURES * Multi-band application for GSM, DCS and PCS cellular phone systems * Low noise and wide dynamic range low IF receiver * More than 35 dB on-chip image rejection in receive mode * More than 64 dB gain control range in receive mode * Integrated channel filter * Integrated TX low-pass filter * High precision I/Q modulator * Multi-band TX modulation loop architecture including offset mixer and phase-frequency detector * Dual PLL with on-chip fully integrated IF VCO * Fully differential design minimizing crosstalk and spurious signals * Functional down to 2.4 V and up to 3.6 V * 3-wire serial bus interface * LQFP48 package. APPLICATIONS * GSM 900 MHz, DCS 1800 MHz and PCS 1900 MHz hand-held transceivers. GENERAL DESCRIPTION The UAA3535HL is intended for Global Systems for Mobile communication (GSM), Digital Cellular communication Systems (DCS) and Personal Communication Services (PCS). The circuit integrates the receiver and most of the transmitter section of hand-held transceivers for these applications. The receiver consists of two sections. The first section is the RF receiver front-end, which amplifies the GSM, DCS or PCS aerial signal, then converts the chosen channel down to a low Intermediate Frequency (IF) of 100 kHz, and also provides more than 35 dB image suppression. Some selectivity is provided at this stage by an on-chip low-pass filter and channel selectivity is provided by a high performance integrated band-pass filter. ORDERING INFORMATION TYPE NUMBER UAA3535HL PACKAGE NAME LQFP48 DESCRIPTION
UAA3535HL
The second section is the IF section, which further amplifies the chosen channel and performs gain control to adjust the output level to the desired value. The IF gain can be varied over more than 64 dB gain range. The transmitter also consists of two sections. The first is a high precision I/Q modulator which converts the baseband modulation up to the transmit IF. The second is a modulation loop architecture which converts the signal to RF. The Local Oscillator (LO) signals are provided by an on-chip Voltage Controlled Oscillator (VCO) for operation of the IF section and are provided externally for operation of the RF section. The frequencies of the RF and IF VCOs are set by internal PLL circuits, which are programmable via a 3-wire serial bus. Comparison frequencies are 200 kHz (100 kHz step programmability) and 13 MHz for the RF and IF PLL respectively, and are derived from a 13 MHz reference signal which has to be supplied externally. The quadrature-phase RF LO signals required for I/Q mixers in reception are generated internally. The quadrature LO signals required for operation of the I/Q modulator are generated inside the IF VCO. The circuit can be powered-up into one of three different modes: RX, TX or SYN mode, depending on the logic state of pins RXON, TXON and SYNON, respectively. It is also possible to set the IC in one of these modes by software, using the 3-wire bus serial programming. In RX (TX) mode, all sections required for receive (transmit) are turned on. The SYN mode is used to power-up the synthesizers prior to the RX or TX mode. In the SYN mode, some internal LO buffers are also powered-up in such a way that VCO pulling is minimized when switching on the receiver or the transmitter. Additional band selection is done using the 3-wire bus serial programming, allowing the required enabling of the Low Noise Amplifiers (LNAs) and charge pumps current programming.
VERSION SOT313-2
plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
2000 Feb 17
2
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
BLOCK DIAGRAM
UAA3535HL
handbook, full pagewidth
RFGND1 GSMIA GSMIB RFGND2 VCC(RF) DCSPCSIA DCSPCSIB RFLOGND VCC(RFLO) RFLOIA RFLOIB
38 39 40 41 37 42 43 29 32 30 31 1 : 1/2 MAIN DIVIDER PHASE-FREQUENCY DETECTOR AND CHARGE PUMP REFERENCE DIVIDER 1 : 1/2 3-WIRE BUS CONTROL REGISTER QUAD
x
7 8 36 35 34 33 9 10 16 17 18 11 12 25 22 3 5 14 15 20
IA IB IFCIA IFCIB IFCQA IFCQB QA QB DATA CLK E RXON TXON SYNON REFIN TXIFA TSTO VCC2(IF) IFGND2 IFCPO IFCPGND VCC(IFCP) IFGND1 IFTUNE VCC1(IF) SYNGND VCC(SYN)
x
RFCPO
24
POWER ENABLE
RFCPGND VCC(RFCP) RFGND3 TXRFI VCC(TXCP) TXCPO
23 26 44 45 2 1
x
PHASE-FREQUENCY DETECTOR AND CHARGE PUMP
PHASE-FREQUENCY DETECTOR AND CHARGE PUMP
1 : 6/7
x
1 : 1/2
21 19 4 13 6
TXCPGND RFGND4 EXTRES
48 46 47
UAA3535HL
x
91 MHz GSM/DCS 78 MHz PCS
28 27
FCA074
Fig.1 Block diagram.
2000 Feb 17
3
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
PINNING SYMBOL TXCPO VCC(TXCP) TXIFA IFGND1 TSTO VCC1(IF) IA IB QA QB RXON TXON IFTUNE VCC2(IF) IFGND2 DATA CLK E VCC(IFCP) IFCPO IFCPGND REFIN RFCPGND RFCPO SYNON PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 DESCRIPTION transmit modulation loop GSM charge pump output transmit modulation loop charge pump supply voltage transmit IF test pin IF ground 1 test mode output IF supply voltage 1 I path A baseband input/output I path B baseband input/output Q path A baseband input/output Q path B baseband input/output RX mode control input TX mode control input transmit IF VCO tune input IF supply voltage 2 IF ground 2 3-wire bus data input 3-wire bus clock input 3-wire bus enable control input (active LOW) transmit IF charge pump supply voltage transmit IF charge pump output transmit IF charge pump ground synthesizers reference input RF charge pump ground RF charge pump output SYN mode control input TXCPGND 48 EXTRES 47 DCSPCSIA DCSPCSIB RFGND3 TXRFI RFGND4 42 43 44 45 46 GSMIA GSMIB RFGND2 39 40 41
UAA3535HL
SYMBOL VCC(RFCP) VCC(SYN) SYNGND RFLOGND RFLOIA RFLOIB VCC(RFLO) IFCQB IFCQA IFCIB IFCIA VCC(RF) RFGND1
PIN 26 27 28 29 30 31 32 33 34 35 36 37 38
DESCRIPTION RF charge pump supply voltage synthesizers supply voltage synthesizers ground RF LO ground RF LO input A RF LO input B RF LO supply voltage RX IF Q test pin B RX IF Q test pin A RX IF I test pin B RX IF I test pin A RF front-end and transmit modulation loop supply voltage RF front-end and transmit modulation loop ground 1 receiver GSM RF input A receiver GSM RF input B RF front-end and transmit modulation loop ground 2 receiver DCS/PCS RF input A receiver DCS/PCS RF input B RF front-end and transmit modulation loop ground 3 input from RF transmit VCOs RF front-end and transmit modulation loop ground 4 reference resistor for transmit modulation loop transmit modulation loop charge pump ground
2000 Feb 17
4
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
UAA3535HL
46 RFGND4
38 RFGND1
41 RFGND2
37 VCC(RF)
44 RFGND3
47 EXTRES
handbook, full pagewidth
42 DCSPCSIA
43 DCSPCSIB
48 TXCPGND
40 GSMIB
39 GSMIA
45 TXRFI
TXCPO
1
36 IFCIA 35 IFCIB 34 IFCQA 33 IFCQB 32 VCC(RFLO)
VCC(TXCP) 2 TXIFA 3 IFGND1 4 TSTO 5 VCC1(IF) 6 IA 7 IB 8 QA 9 QB 10 RXON 11 TXON 12
UAA3535HL
31 RFLOIB 30 RFLOIA 29 RFLOGND 28 SYNGND 27 VCC(SYN) 26 VCC(RFCP) 25 SYNON
IFCPGND 21
IFTUNE 13
VCC2(IF) 14
IFGND2 15
VCC(IFCP) 19
RFCPGND 23
RFCPO 24
REFIN 22
DATA 16
CLK 17
E 18
IFCPO 20
FCA068
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION RF receiver The receiver front-end converts the aerial RF signal from EGSM (Extended GSM; 925 to 960 MHz), DCS (1805 to 1880 MHz) or PCS (1930 to 1990 MHz) bands down to an IF signal of 100 kHz. The first stages are symmetrical LNAs that are matched to 50 using external baluns. The LNAs are followed by an I/Q down-mixer. The I/Q down-mixer consists of two mixers in parallel but driven by quadrature out of phase LO signals. The In-phase (I) and Quadrature- phase (Q) IF signals are then low-pass filtered to provide protection from high frequency offset interferers. The IF I and Q signals are then fed into the channel filter.
Channel filter and AGC The front-end IF I and Q outputs are first applied to an amplifier circuit with provision for three 8 dB gain step adjustment possibilities and then to an integrated band-pass channel filter. The filter is a fifth-order band-pass filter centred around 100 with 220 kHz bandwidth. After filtering the IF I and Q signals are further amplified with provision for eleven 4 dB gain steps and DC offset compensation. I/Q modulator I and Q baseband signals are applied to the I/Q modulator where the modulation spectrum is shifted up to the transmit IF frequency. For low harmonic distortion, low carrier leakage and high image rejection, the phase error must be kept as small as possible. The IF output of the modulator is fed to an integrated low-pass filter where unwanted spurious signals are suppressed, prior to being fed to the phase detector. 5
2000 Feb 17
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
Transmit modulation loop The analog transmit modulation loop consists of an on-chip offset mixer, a phase-frequency detector, an off-chip loop filter and a transmit VCO. The analog PLL copies the modulation to the off-chip transmit VCO and acts as a tracking filter. A PLL of at least third-order is required to meet noise requirements at 20 MHz offset from the carrier. The PLL bandwidth must be greater than 600 kHz in order to keep a low dynamic phase error and to minimize the acquisition time. RF and IF LO sections The RF LO input covering the 1788 to 2002 MHz bandwidth is connected to an external RF VCO module. The RF LO section includes the LO buffering for the RF PLL, a divider-by-2 or 1 for GSM and DCS/PCS respectively which drives a quadrature generation network for use in the RX I/Q down-mixer or the transmit modulation loop offset mixer. The IF LO section consists of a fully integrated IF VCO which internally provides the I/Q modulator with the necessary quadrature signals. Dual PLL A high performance dual PLL is included on-chip which enables the frequencies of the RF VCO to be synthesized off-chip and that of the IF VCO on-chip. Very low close-in phase noise is achieved which allows the PLL loop bandwidth to be widened to achieve a shorter settling time. The charge pump circuit has very low leakage current, in the nA range, so that the spurious signals are hardly detectable. Table 1 Basic operating mode control CONTROL PIN LEVEL MODE SYNON SYN RX TX Idle HIGH HIGH HIGH LOW RXON LOW HIGH LOW LOW TXON LOW LOW HIGH LOW SYNTHESIZER on on on off RECEIVER off on off off
UAA3535HL
The `main' path consists of a programmable divider chain that divides the RF and IF LO signals down to frequencies of 200 kHz (100 kHz step programmability) and 13 MHz respectively. Their phase is then compared in a digital Phase-Frequency Detector (PFD) with that of a reference signal derived from an external 13 or 26 MHz clock signal. The phase error information is fed back to the VCO via the charge pump circuit that `sinks' into or `sources' current from the loop filter capacitor, thereby changing the VCO frequency so that the loop becomes `phase locked'. Operating modes BASIC OPERATING MODES The circuit can be powered-up into different operating modes depending on the voltage level applied at pins RXON, TXON and SYNON (hardware control). This defines the three main modes; RX, TX and SYN. Table 1 describes the different operating modes as defined by hardware control. The operation mode status depends on the control bits SYNON, RXON and TXON (see Table 1). When the receiver is on, it is possible to switch-off the low noise amplifier to perform DC offset compensation in the receiver (see Section "LNA power control"). When in TX mode, it is possible to enable the IF synthesizer and VCO independently from the rest of the TX section via bit TXIFON via the control bus.
POWER STATUS TRANSMITTER off off on off
2000 Feb 17
6
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
IF SYNTHESIZER AND VCO CONTROL The IF synthesizer is only necessary in transmit mode. The TX IF VCO and synthesizer section can be powered-up with the control bit TXIFON; see Table 2. If TXIFON is not used, the IF VCO and synthesizer section will be enabled with the signal TXON. Table 2 IF synthesizer and VCO power control BIT TXIFON 0 1 LNA POWER CONTROL When the receiver is on, it is possible to switch-off the low noise amplifier separately. Separate control of the low noise amplifier is accomplished by the control bit LNA; see Table 3. Table 3 LNA power control BIT LNA 0 1 BAND SELECTION CONTROL The receiver includes two RF front-end and RF LO sections; one for GSM where the RF LO is divided-by-2 and fed to the 925 to 960 MHz front-end, and the other one for DCS and/or PCS where the RF LO is not divided and fed to the 1805 to 1990 MHz front-end. The selection of these 2 modes is accomplished by the control bit BND; see Table 4. Table 4 Band selection control BIT BND 0 1 GSM DCS and/or PCS BAND MODE LNA MODE off on TX CHARGE PUMP CURRENT CONTROL IF SYNTHESIZER AND VCO MODE off on SIDEBAND SELECTION CONTROL
UAA3535HL
The receiver includes an image rejection front-end which allows the use of a RF LO 100 kHz below the RF input frequency (infradyne) or 100 kHz above the RF input frequency (supradyne). Between these two states the proper image should be selected for rejection. The selection of these 2 modes is accomplished by the control bit SBD; see Table 5. Table 5 Sideband selection control SIDEBAND MODE supradyne infradyne
BIT SBD 0 1
The transmit modulation loop includes a transmit charge pump where sink and source currents are determined by an external resistor. When determined, this nominal current can be divided-by-1 or 2 to cope with different transmit VCO gains. The selection of these 2 modes is accomplished by the control bit TXI; see Table 6. Table 6 TX charge pump current control TX CHARGE PUMP CURRENT MODE nominal current nominal current divided-by-2
BIT TXI 0 1
REFERENCE DIVIDER CONTROL The reference divider can be programmed to divide the external reference frequency by 65 or 130. The selection of these 2 modes is accomplished by the control bit REFDIV; see Table 7. Table 7 Reference divider control REFERENCE DIVIDER MODE divide-by-65 divide-by-130
BIT REFDIV 0 1
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7
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
IF DIVIDER CONTROL The IF divider can be programmed to divide the integrated IF VCO frequency by 1 or 2. The selection of these 2 modes is accomplished by the control bit IFDIV; see Table 8. Table 8 IF divider control BIT IFDIV 0 1 TXIF FILTER CONTROL The transmit section integrates two switchable low-pass filters, one for a 45.5 MHz IF and the other one for 91 MHz IF. The selection of these 2 modes is accomplished by the control bit FILT; see Table 9. Table 9 TXIF filter control BIT FILT 0 1 TXIF FILTER MODE IF 45.5 MHz IF 91 MHz IF DIVIDER MODE IF = fVCO IF = fVCO divided by 2 Programming SERIAL PROGRAMMING BUS
UAA3535HL
A simple 3-wire unidirectional serial bus is used to program the circuit. The 3 lines are DATA, CLK and E (enable). The data sent to the device is loaded in bursts framed by E. Programming clock edges are ignored until E goes active LOW. The programmed information is loaded into the addressed latch when E returns inactive HIGH. This is allowed when CLK is in either state without causing any consequences to the register data. Only the last 17 bits serially clocked into the device are retained within the programming register. Additional leading bits are ignored, and no check is made on the number of clock pulses. The fully static CMOS design uses virtually no current when the bus is inactive. It can always capture new programming data even during power-down of both synthesizers. DATA FORMAT Data is entered with the most significant bit first. The leading bits make up the data field, while the trailing 4 bits are an address field. The address bits are decoded on the rising edge of E. This produces an internal load pulse to store the data in the addressed latch. To ensure that data is correctly loaded on first power-up, E should be held LOW and only taken High after having programmed an appropriate register. To avoid erroneous divider ratios, the pulse is inhibited during the period when data is read by the frequency dividers. This condition is guaranteed by respecting a minimum E pulse width after data transfer. The allocation of the register bits is given in Table 11. REGISTER PRESET CONDITIONS The UAA3535HL programming registers have a preset state. The preset values can be found in Table 12. Conditions for guaranteed preset values at power-on are as follows: * DATA, CLOCK, E, SYNON, RXON and TXON must be at 0 V * Preset value is guaranteed 2 ms after VCC(SYN) rises to 90% of 2.6 V * E should stay at 0 V up to the end of the first programming word.
IF SYNTHESIZER DIVIDER CONTROL The IF synthesizer divider can be programmed to divide the semi-integrated IF VCO frequency by 6 or 7. The selection of these 2 modes is accomplished by the control bit IFO; see Table 10. Table 10 IF synthesizer divider control BIT IFO 0 1 IF SYNTHESIZER DIVIDER MODE divide-by-6 divide-by-7
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Table 11 Register bit allocation; notes 1 and 2 and 3
2000 Feb 17 9
Philips Semiconductors
Low power GSM/DCS/PCS multi-band transceiver
REGISTER ALLOCATION DATA FIELD BIT 16 X X X BIT 15 X X X BIT 14 RF 14 X X BIT 13 RF 13 X 0 BIT 12 RF 12 X FILT BIT 11 RF 11 0 REF DIV BIT 10 RF 10 0 IFO BIT 9 RF 9 0 IF DIV BIT 8 RF 8 0 TXI BIT 7 RF 7 0 SBD BIT 6 RF 6 LNA BND BIT 5 RF 5 G5 1 BIT 4 RF 4 G4 1 BIT 3 RF 3 G3 TXIF ON BIT 2 RF 2 G2 SYN ON BIT 1 RF 1 G1 RX ON BIT 0 RF 0 G0 TX ON ADDRESS FIELD LAST 4 BITS 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0
for test purpose only; bit usage to be defined; this is a forbidden address Notes 1. The 15-bit RF divider is programmable through the 15 bits RF0 to RF14, in steps of 100 kHz. 2. X = don't care. 3. The 6-bit AGC attenuator is programmable through the 6 bits G0 to G5 in 17 steps of 4 dB (see Table 13). Table 12 Preset values; note 1 REGISTER ALLOCATION DATA FIELD BIT 16 X X X BIT 15 X X X BIT 14 1 X X BIT 13 0 X 0 BIT 12 0 X 0 BIT 11 1 0 0 BIT 10 0 0 1 BIT 9 1 0 1 BIT 8 0 0 0 BIT 7 0 0 1 BIT 6 0 1 0 BIT 5 0 1 1 BIT 4 0 1 1 BIT 3 0 1 0 BIT 2 1 1 0 BIT 1 1 1 0 BIT 0 0 1 0
ADDRESS FIELD LAST 4 BITS 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0
for test purpose only; bit usage to be defined; this is a forbidden address Note 1. X = don't care.
Objective specification
UAA3535HL
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
Table 13 AGC gain look-up table; note 1 G5(2) 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Notes 1. Codes not included in the table are forbidden. 2. Steps at the input of the band-pass filter. G4(2) 1 1 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 G3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 G2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 G1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 1 1 0 0 G0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
UAA3535HL
ATTENUATION (dB)(3) 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68
3. The figure represents the total attenuation in the receive path, with respect to the maximum gain.
2000 Feb 17
10
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
LIMITING VALUES SYMBOL VCC VCC(TXCP); VCC(RFCP) Pmax Tamb Tstg supply voltage supply voltage for RX and TX charge pumps maximum power dissipation ambient temperature storage temperature DESCRIPTION
UAA3535HL
MIN. -0.3 -0.3 - -30 -40
MAX. +3.6 +4.25 1 +70 +150
UNIT V V W C C
THERMAL CHARACTERISTICS SYMBOL Rth(j-c) PARAMETER thermal resistance from junction to case VALUE 65 UNIT K/W
DC CHARACTERISTICS VCC = VCC(TXCP) = VCC(RFCP) = 2.6 V; Tamb = 25 C; unless otherwise specified. SYMBOL ICC PARAMETER supply current CONDITIONS normal mode; total power-down; note 1 preset mode; total power-down; note 2 RX and SYN mode TX, TXIF and SYN mode SYN mode TXIF and SYN mode VCC(RF) RF front-end and transmit modulation loop supply voltage RF front-end and transmit modulation loop supply current RX mode; one LNA and quadrature mixer active RX mode; one LNA active TX mode; transmit modulation loop active without charge pump VCC1(IF) ICC1(IF) IF supply voltage 1 IF supply current 1 RX mode; I/Q low IF band-pass filter active TX mode; I/Q modulator active VCC2(IF) ICC2(IF) IF supply voltage 2 IF supply current 2 RX mode; I/Q AGC active TXIF mode; TX IF VCO active - - - - - - 2.4 MIN. TYP. 10 100 51.5 54 17 29 - MAX. 50 200 60 66 20 37 3.3 UNIT A A mA mA mA mA V
ICC(RF)
- - - 2.4 - - 2.4 - -
17 6 6 - 7 9 - 4 9
- - - 3.3 - - 3.3 - -
mA mA mA V mA mA V mA mA
2000 Feb 17
11
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
UAA3535HL
SYMBOL VCC(RFLO) ICC(RFLO)
PARAMETER RF LO supply voltage RF LO supply current
CONDITIONS RX and SYN mode; RF LO buffer - and divider section active TX and SYN mode; RF LO buffer - and divider section active SYN mode; RF LO buffer active -
MIN. 2.4 -
TYP. 10 10 6 - 9.5 0.5 - 1.5 - 1.0
MAX. 3.3 - - - 3.3 - - 3.3 - 4.25 -
UNIT V mA mA mA V mA mA V mA V mA
VCC(SYN) ICC(SYN)
synthesizers supply voltage synthesizers supply current SYN mode; RF synthesizer active
2.4 -
TXIF mode; IF synthesizer active - VCC(IFCP) ICC(IFCP) VCC(TXCP) ICC(TXCP) transmit IF charge pump supply voltage transmit IF charge pump supply current transmit modulation loop charge pump supply voltage transmit modulation loop charge pump supply current RF charge pump supply voltage RF charge pump supply current SYN mode; RF LO charge pump active; in lock TX mode; TX RF charge pump active; in lock; external resistance is 1800 TXIF mode; IF LO charge pump active; in lock 2.4 - 2.4 -
VCC(RFCP) ICC(RFCP)
2.4 -
- 4.5
4.25 -
V mA
Baseband section: pins IA, IB, QA and QB VI(CM) VQ(CM) common mode input-output voltage I common mode input-output voltage Q V IA + V IB V I = ----------------------2 V QA + V QB V Q = --------------------------2 1.15 1.15 1.25 1.25 1.35 1.35 V V
Logic input levels: pins DATA, CLK, E, TXON, RXON and SYNON VIH VIL Notes 1. VCC(TXCP) = VCC(RFCP) = 4.2 V; pins TXON, RXON and SYNON are HIGH impedance; pins DATA, CLK and E are HIGH impedance. 2. VCC(TXCP) = VCC(RFCP) = 4.2 V; pins TXON, RXON and SYNON are LOW; pins DATA, CLK and E are HIGH. HIGH-level input voltage LOW-level input voltage 0.9 - - - - 0.3 V V
2000 Feb 17
12
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
AC CHARACTERISTICS VCC = VCC(CP) = 2.6 V; Tamb = -30 to +70 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP.
UAA3535HL
MAX.
UNIT
RF receiver section; measured in a 50 impedance system, including external input baluns and matching networks to 50 PINS: GSMIA AND GSMIB fi(RF) Ri(dif) Ci(dif) F off Poff DES3i RF input frequency differential input resistance differential input capacitance noise figure LNA off-state attenuation input referred 3 dB desensitization parallel RC input model parallel RC input model for Ri; maximum AGC; notes 1 and 2 bit LNA = 0; note 1 f = 3 MHz; Tamb = 25 C; note 1 925 - - - - -25 - 75 1.5 3.5 45 - - 960 - - 4 - - - MHz pF dB dB dBm dBm
LNA off-state power handling bit LNA = 0; notes 1 and 3 3
PINS: DCSPCSIA AND DCSPCSIB fi(RF) Ri(dif) Ci(dif) F off Poff DES3i RF input frequency differential input resistance differential input capacitance noise figure LNA off-state attenuation input referred 3 dB desensitization parallel RC input model parallel RC input model for Ri; maximum AGC; notes 1 and 2 bit LNA = 0; note 1 f = 3 MHz; Tamb = 25 C; note 1 1805 - - - - -28 - 120 1.0 4 45 - - 1990 - - 4.5 - - - MHz pF dB dB dBm dBm
LNA off-state power handling bit LNA = 0; notes 1 and 3 6
PINS: GSMIA, GSMIB, DCSPCSIA AND DCSPCSIB s11 SPURP(RFin) input reflection coefficient power level of spurious signals at RF input note 2 900 to 1000 MHz band 1800 to 2000 MHz band out of preceding bands CP1 IP3i IP2i DES3i IR Gv(RF) 1 dB input compression point minimum AGC; Tamb = 25 C; note 1 input referred third-order intercept input referred second-order intercept input referred 3 dB desensitization image rejection gain mismatch GSM and DCS paths maximum AGC; Tamb = 25 C; note 1 maximum AGC; note 4 f = 3 MHz; Tamb = 25 C; note 1 fIF = 200 kHz; Tamb = 25 C; note 1 note 5 - - - - -25 -18 - -23 35 - -15 - - - - - 30 - 38 - -10 -57 -47 -45 - - - - - 2 dB dBm dBm dBm dBm dBm dBm dBm dB dB
2000 Feb 17
13
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
UAA3535HL
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
PINS IA, IB, QA AND QB (RX MODE) Gv(min) Gv(max) Gv(step) Gv(I/Q) LEAGC Vo(peak) Io(peak) Voffset HP-3dB BIF(-3dB) td(g) 5(IF) minimum voltage conversion gain gain set to minimum; notes 1 and 5 19 89 - - - 25 93 4 - - - - - 50 - 6 - 1.5 31 64 82 31 97 - 0.5 5 +2 +0.5 - - +300 8 250 2 - - - dB dB dB dB deg dB dB V A mV kHz kHz s dB dB dB
maximum voltage conversion gain set to maximum; gain notes 1 and 5 voltage conversion gain step gain mismatch I and Q paths quadrature-phase error I and Q paths gain control linearity maximum output voltage per pin maximum output current per pin output offset voltage -3 dB high-pass corner frequency -3 dB IF filter bandwidth group delay variation IF filter attenuation (fifth-order) 100 kHz centre frequency 30 kHz < fo < 170 kHz fo = 100 kHz 200 kHz fo = 100 kHz 400 kHz fo = 100 kHz 600 kHz under static conditions note 5 note 5 peak error
over full gain range; note 2 -2 over any 20 dB gain range -0.5 3% T.H.D.; RL = 100 k per pin 0.75 25 -300 4 220 - 17 54 73
Transmit IF section (initial conditions: Vmod(peak) = 0.5 V; fmod = 67.7 kHz; unless otherwise specified) PINS IA, IB, QA AND QB (TX MODE) fmod Vmod(peak) Ri(D) modulation frequency modulation level dynamic input resistance 3 dB low-pass cut-off frequency single-ended; peak value single-ended 1 - - - 0.5 25 - 30 - - - - 0.55 - MHz V k
IF LO oscillator (measured and guaranteed on demonstration board at Tamb = 25 C) fIFLO KVCO Vtune fVCC fTRON range of possible operation VCO gain tuning voltage frequency variation with respect to the supply voltage frequency variation with programming Vtune from 0.6 V to VCC - 0.6 V referenced to VCC(IFCP) pushing pulling 78 - 0.4 - -5 91 - VCC - 0.4 1 +5 MHz MHz/V V MHz/V kHz
Transmit modulation loop section OFFSET MIXER; PIN TXRFI fRF RF input frequency 880 - 1910 MHz
2000 Feb 17
14
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
UAA3535HL
SYMBOL Ri Ci Pi s11 F CP1 SPURP(RFin)
PARAMETER input resistance input capacitance input power input reflection coefficient noise figure power level of spurious signals at RF input
CONDITIONS single-ended single-ended - -
MIN. -
TYP. 50 -20 -10 10 -20 -50 - 2 - - -17 - - - -45 -45 4
MAX.
UNIT pF dBm dB dB dBm dBm dBm
-23 - Tamb = 25 C LO leakage other - - - - 1
1 dB input compression point Tamb = 25 C
PHASE DETECTOR; PIN TXCPO ICP(max) charge pump maximum sink or source current GSM mode; external resistance of 1800 1% for minimum output current; TXI = 0; note 6 DCS and PCS mode; external resistance of 1800 1% for minimum output current; TXI = 1; note 6 K K Vo Ro Ro(pd) LOo IM3o IMo NOISE phase-frequency detector gain phase-frequency detector gain variation output voltage output resistance output resistance power down local oscillator feedthrough third-order products level image level phase noise output power density V CC(PHD) V o = ---------------------2 TX mode disabled note 7 offset +3 x 67.7 kHz or -3 x 67.7 kHz; note 7 fIFLO - 67.7 kHz; note 7 f = 400 kHz; Tamb = 25 C; note 7 f = 1.8 MHz; Tamb = 25 C; note 7 SPURL(4fm) SPURL(8fm) RF LO buffer RF SOURCE CONNECTED AT PIN RFLOIA AND RFLOIB fi(RF) 2000 Feb 17 RF input frequency 15 1788 - 2002 MHz level of spurious signals at 4 x fmod level of spurious signals at 8 x fmod fmod = 67.7 kHz; notes 7 and 8 fmod = 67.7 kHz; note 7 for ICP = 1 mA over output voltage range mA
0.5
1
2
mA
- - 0.4 - - - - - - -
0.16 - - 10 1 -40 -55 -45 - - - - -
- 10
mA/rad %
VCC(CP) - 0.4 V - - -32 -50 -37 -117 -117 -136 -50 -55 k k dBc dBc dBc dBc/Hz dBc/Hz dBc/Hz dBc dBc
f = 20 MHz; Tamb = 25 C - - -
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
UAA3535HL
SYMBOL Ri(dif) Ci(dif) s11 PLO
PARAMETER differential input resistance differential input capacitance input reflection coefficient power available from the LO source
CONDITIONS parallel RC input model parallel RC input model - - -
MIN.
TYP. 50 0.2 -15 -5 - - -10 -2
MAX.
UNIT pF dB dBm
-8
RF and IF synthesizers REFERENCE INPUT; PIN REFIN fref Vi(rms) Ri fRFLO fcomp(RF) fcomp(leak) fstep(RF) noise SPURP(RF) ICP(nom) K K IL(CP) VCP Ro reference frequency input voltage level (RMS value) input resistance fref = 13 MHz REFDIV = 0 REFDIV = 1 - - 60 - 1700 - with recommended loop filter fcomp(RF) = 200 kHz f = 2 kHz f > 400 kHz sink or source ICP = 2 mA over VCP range - - - - 1.7 - - -5 0.4 - 13 26 - 10 - 200 -50 100 -80 - 2.0 0.32 - - - 1 - - 220 - 2100 - - - -76 -70 2.3 - 10 +5 VCC - 0.4 - MHz MHz mV k
RF SYNTHESIZER; PIN RFCPO synthesizer frequency comparison frequency 200 kHz comparison frequency leakage frequency step programmability close-in phase noise power level of spurious signals nominal charge pump output current phase-frequency detector gain phase-frequency detector gain variation charge pump output voltage output resistance MHz kHz dBc kHz dBc/Hz dBc mA mA/rad % nA V k
charge pump leakage current in off state ICP within specified range SYN mode disabled; power-down
2000 Feb 17
16
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
UAA3535HL
SYMBOL
PARAMETER
CONDITIONS
MIN. -
TYP.
MAX.
UNIT
IF SYNTHESIZER; PINS IFTUNE AND IFCPO fIFLO fcomp(IF) noise SPURP(IF) ICP K K IL VCP Ro synthesizer frequency comparison frequency close-in phase noise power level of spurious signals charge pump output current phase-frequency detector gain phase-frequency detector gain variation charge pump output voltage output resistance TXIFON and TXON mode disabled; power-down sink or source for ICP = 1 mA over VCP range f = 400 kHz 70 - - - 0.85 - - -5 0.4 - 100 - -117 -70 1.15 - 10 +5 VCC - 0.4 - MHz MHz dBc/Hz dBc mA mA/rad % nA V k 13 - - 1.0 0.16 - - - 1
charge pump leakage current off state
DIVIDERS RATIOS D/DRF(main) D/DIF(main) RF main divider ratio IF main divider ratio ratio between RFLOI frequency and fcomp(RF) ratio between IF VCO frequency and fcomp(IF) REFDIV = 0 REFDIV = 1 D/DIF(REFDIV) General tON Notes 1. Measured and guaranteed only on OM 5178 demonstration board. 2. This value includes printed-circuit board and balun losses. 3. The power level of the spurious signals in this measurement is less than specified under SPURP(RFin). 4. IP2i related to an IM2 measurement in low gain mode. 5. Voltage gain defined as the differential baseband RMS output voltage (either at pins IA and IB or pins QA and QB measured in standard load) divided by the RMS input voltage at the RF baluns. 6. This range is obtained through variation of the external reference resistor. 7. Measured at external transmit VCO output. 8. This is based on an adjustment in such a way, that a difference of 36 dBc is obtained in the level of the wanted signal at the frequency fIF + fmod and the level of the signal at the frequency 3fIF - fmod, measured at the input of the phase-frequency comparator for IF frequencies of 45.5 and 91 MHz. turn-on time 90% of the final current - - 200 s IF reference divider ratio REFDIV = 0 REFDIV = 1 8940 6 - - - - - - 65 130 1 2 10 010 7 - - - -
D/DRF(REFDIV) RF reference divider ratio
2000 Feb 17
17
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
UAA3535HL
SERIAL TIMING CHARACTERISTICS Initial parameter values: VCC = 2.6 V 5%; Tamb = -30 to +70 C; unless otherwise specified; see Fig.3. SYMBOL Serial programming clock: pin CLK tr tf Tcy tsu(E) th(E) tW(E) tsu(E) tsu(D) th(D) rise time fall time clock cycle time - - 200 10 10 - - - - - - - 20 20 - - - - - - - ns ns ns PARAMETER MIN. TYP. MAX. UNIT
Enable programming: pin E delay to rising clock edge delay from last falling clock edge minimum inactive pulse width enable set-up time to next clock edge 200 100 4000 200 ns ns ns ns
Register serial input data: pin DATA input data to clock set-up time input data to clock hold time 50 50 ns ns
tSU;DAT handbook, full pagewidth
tHD;DAT
Tcy
tf
tr
tEND tSU;E
CLK
DATA
MSB
LSB
ADDRESS
E tSTART
MGD565
tW(min)
Fig.3 Timing diagram 3-wire serial bus.
2000 Feb 17
18
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RFGND1 DCSRX BALUN 38 39 40 41 37 42 GSMRX BALUN RFLOGND VCC(RFLO) BALUN GSM/DCS/PCS 24 PHASE-FREQUENCY DETECTOR AND CHARGE PUMP REFERENCE DIVIDER 1 : 1/2 POWER ENABLE 43 29 32 30 31 1 : 1/2 MAIN DIVIDER 3-WIRE BUS CONTROL REGISTER QUAD
APPLICATION INFORMATION
Philips Semiconductors
handbook, full pagewidth
Low power GSM/DCS/PCS multi-band transceiver
x
7 8 36 35 34 33 9 10 16 17 18 11 12 25 22 3 5 14 15 20 IFCIA IFCIB IFCQA IFCQB
IA IB
PCSRX
RFGND2 VCC(RF)
x
QA QB DATA CLK E RXON TXON SYNON REFIN TXIFA TSTO VCC2(IF) IFGND2 IFCPO IFCPGND VCC(IFCP) IFGND1 IFTUNE VCC1(IF) 13 MHz VTCXO
19
RFCPGND VCC(RFCP) RFGND3 23 26 44 45 VCC(TXCP) GSMTX DCSTX TXCPGND PCSTX RFGND4 EXTRES 48 2 1 46 47
x
PHASE-FREQUENCY DETECTOR AND CHARGE PUMP
PHASE-FREQUENCY DETECTOR AND CHARGE PUMP
1 : 6/7
x
1 : 1/2
21 19 4 13 6
UAA3535HL
Objective specification
x
91 MHz GSM/DCS 78 MHz PCS
28 27
FCA075
UAA3535HL
SYNGND VCC(SYN)
Fig.4 Application diagram.
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
PACKAGE OUTLINE LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
UAA3535HL
SOT313-2
c
y X
36 37
25 24 ZE
A
e
E HE
A A2
A1
(A 3) Lp L detail X
wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC 136E05 JEDEC MS-026 EIAJ EUROPEAN PROJECTION A max. 1.60 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1.0 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 0o
o
ISSUE DATE 99-12-27 00-01-19
2000 Feb 17
20
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
UAA3535HL
* For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2000 Feb 17
21
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable suitable suitable suitable suitable suitable
UAA3535HL
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
2000 Feb 17
22
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
NOTES
UAA3535HL
2000 Feb 17
23
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 69
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
403506/01/pp24
Date of release: 2000
Feb 17
Document order number:
9397 750 06172

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